Polysilicon capacitors and electrodes are well known in the integrated circuitry art. In a conventional electrically programmable read-only memory (EPROM) or an erasable electrically-programmable read-only memory (EEPROM), polysilicon is used to form a floating gate electrode over a gate region, the floating gate electrode further being capacitively coupled to a connected gate electrode. Such floating gate electrodes are generally formed over a thin gate insulator layer and adjacent thicker field oxide layers. A second, thin gate insulator layer is deposited on, or grown from the polysilicon. The connected gate electrode, or control gate, which can be made out of various conductive materials such as polysilicon or metal, is then deposited over the floating gate.
For proper gate electrode operation, it is desirable to maximize the capacitance between the floating gate electrode and the connected gate electrode relative to the capacitance between the floating gate electrode and the gate region in the semiconductor layer. In the past, this has been done by controlling the thickness of the oxide layer between the floating gate electrode and the connected gate electrode. This method of controlling the relative capacitance values has, however, physical limits, especially as the size of the gates involved shrink. In an EPROM configuration, the polysilicon gate must be close enough to the semiconductor substrate in order to receive hot electrons by injection, and therefore, the capacitance between the floating gate electrode and the semiconductor substrate cannot be-diminished beyond a certain point. The capacitance between the connected electrode and the floating gate electrode can be increased by decreasing the thickness of the intervening insulator to approximately 350 angstroms or less, but it cannot be decreased beyond a certain limit because leakage through the insulator between the floating gate and the control gate will increase to the point of causing poor data retention.
Therefore, a need has arisen in the industry for a new method of improving the capacitive coupling of a floating gate electrode to an upper gate relative to the capacitance of the floating gate electrode and the semiconductor substrate. Further, a need has arisen in the industry to find methods of improving capacitive coupling in the face of shrinking areas that can be devoted to the fabrication of capacitors.